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TMS320DM368

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TMS320DM368

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产品详情

DSP type 0 Operating system Linux Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) -40 to 85
DSP type 0 Operating system Linux Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) -40 to 85
NFBGA (ZCE) 338 169 mm² 13 x 13
  • Highlights
    • High-Performance Digital Media System-on-Chip (DMSoC)
    • 432-MHz ARM926EJ-S Clock Rate
    • Two Video Image Co-processors (HDVICP, MJCP) Engines
    • Supports a Range of Encode, Decode and Video Quality Operations
    • Video Processing Subsystem
      • HW Face Detect Engine
      • Resize Engine from 1/16x to 8x
      • 16-Bit Parallel AFE (Analog Front-End) Interface Up to 120 MHz
      • 4:2:2 (8-/16-bit) Interface
      • 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output
      • 3 DACs for HD Analog Video Output
      • Hardware On-Screen Display (OSD)
    • Capable of 1080p 30fps H.264 video processing
    • Peripherals include EMAC, USB 2.0 OTG, DDR2/NAND, 5 SPIs, 2 UARTs, 2 MMC/SD/SDIO, Key Scan
    • 8 Different Boot Modes and Configurable Power-Saving Modes
    • Pin-to-pin and software compatible with DM365
    • Extended temperature (-40°C - 85°C) available
    • 3.3-V and 1.8-V I/O, 1.35-V Core
    • 338-Pin Ball Grid Array at 65nm Process Technology
  • High-Performance Digital Media System-on-Chip (DMSoC)
    • 432-MHz ARM926EJ-S Clock Rate
    • 4:2:2 (8-/16-Bit) Interface
    • Capable of 1080p 30fps H.264 video processing
    • Pin compatible with DM365 processors
    • Fully Software-Compatible With ARM9™
    • Extended temperature available for 432-Mhz device
  • ARM926EJ-S™ Core
    • Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
    • DSP Instruction Extensions and Single Cycle MAC
    • ARM® Javelle® Technology
    • Embedded ICE-RT Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • 32K-Byte RAM
    • 16K-Byte ROM
    • Little Endian
  • Two Video Image Co-processors (HDVICP, MJCP) Engines
    • Support a Range of Encode and Decode Operations
    • H.264, MPEG4, MPEG2, MJPEG, JPEG, WMV9/VC1
  • Video Processing Subsystem
    • Front End Provides:
      • HW Face Detect Engine
      • Hardware IPIPE for Real-Time Image Processing
        • Resize Engine
          • Resize Images From 1/16x to 8x
          • Separate Horizontal/Vertical Control
          • Two Simultaneous Output Paths
      • IPIPE Interface (IPIPEIF)
      • Image Sensor Interface (ISIF) and CMOS Imager Interface
      • 16-Bit Parallel AFE (Analog Front End) Interface Up to 120 MHz
      • Glueless Interface to Common Video Decoders
      • BT.601/BT.656/BT.1120 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
      • Histogram Module
      • Lens distortion correction module (LDC)
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • Composite NTSC/PAL video encoder output
      • 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output
      • 3 DACs for HD Analog Video Output
      • LCD Controller
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
  • Analog-to-Digital Convertor (ADC)
  • Power Management and Real Time Clock Subsystem (PRTCSS)
    • Real Time Clock
  • 16-Bit Host-Port Interface (HPI)
  • 10/100 Mb/s Ethernet Media Access Controller (EMAC) - Digital Media
    • IEEE 802.3 Compliant
    • Supports Media Independent Interface (MII)
    • Management Data I/O (MDIO) Module
  • Key Scan
  • Voice Codec
  • External Memory Interfaces (EMIFs)
    • DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O)
    • Asynchronous16-/8-bit Wide EMIF (AEMIF)
      • Flash Memory Interfaces
        • NAND (8-/16-bit Wide Data)
        • 16 MB NOR Flash, SRAM
        • OneNAND(16-bit Wide Data)
  • Flash Card Interfaces
    • Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
    • SmartMedia/xD
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • USB Port with Integrated 2.0 High-Speed PHY that Supports
    • USB 2.0 High-Speed Device
    • USB 2.0 High-Speed Host (mini-host, supporting one external device)
    • USB On The Go (HS-USB OTG)
  • Four 64-Bit General-Purpose Timers (each configurable as two 32-bit timers)
  • One 64-Bit Watch Dog Timer
  • Two UARTs (One fast UART with RTS and CTS Flow Control)
  • Five Serial Port Interfaces (SPI) each with two Chip-Selects
  • One Master/Slave Inter-Integrated Circuit(I2C) Bus™
  • One Multi-Channel Buffered Serial Port (McBSP)
    • I2S
    • AC97 Audio Codec Interface
    • S/PDIF via Software
    • Standard Voice Codec Interface (AIC12)
    • SPI Protocol (Master Mode Only)
    • Direct Interface to T1/E1 Framers
    • Time Division Multiplexed Mode (TDM)
    • 128 Channel Mode
  • Four Pulse Width Modulator (PWM) Outputs
  • Four RTO (Real Time Out) Outputs
  • Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
  • Boot Modes
    • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, UART, USB, SPI, EMAC, or HPI
    • AEMIF (NOR and OneNAND)
  • Configurable Power-Saving Modes
  • Crystal or External Clock Input (typically 19.2 Mhz, 24 MHz, 27 Mhz or 36 MHz)
  • Flexible PLL Clock Generators
  • Debug Interface Support
    • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
    • ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory
    • Device Revision ID Readable by ARM
  • 338-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch
  • 65nm Process Technology
  • 3.3-V and 1.8-V I/O, 1.35-V Internal
  • Community Reesources

All trademarks are the property of their respective owners.

  • Highlights
    • High-Performance Digital Media System-on-Chip (DMSoC)
    • 432-MHz ARM926EJ-S Clock Rate
    • Two Video Image Co-processors (HDVICP, MJCP) Engines
    • Supports a Range of Encode, Decode and Video Quality Operations
    • Video Processing Subsystem
      • HW Face Detect Engine
      • Resize Engine from 1/16x to 8x
      • 16-Bit Parallel AFE (Analog Front-End) Interface Up to 120 MHz
      • 4:2:2 (8-/16-bit) Interface
      • 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output
      • 3 DACs for HD Analog Video Output
      • Hardware On-Screen Display (OSD)
    • Capable of 1080p 30fps H.264 video processing
    • Peripherals include EMAC, USB 2.0 OTG, DDR2/NAND, 5 SPIs, 2 UARTs, 2 MMC/SD/SDIO, Key Scan
    • 8 Different Boot Modes and Configurable Power-Saving Modes
    • Pin-to-pin and software compatible with DM365
    • Extended temperature (-40°C - 85°C) available
    • 3.3-V and 1.8-V I/O, 1.35-V Core
    • 338-Pin Ball Grid Array at 65nm Process Technology
  • High-Performance Digital Media System-on-Chip (DMSoC)
    • 432-MHz ARM926EJ-S Clock Rate
    • 4:2:2 (8-/16-Bit) Interface
    • Capable of 1080p 30fps H.264 video processing
    • Pin compatible with DM365 processors
    • Fully Software-Compatible With ARM9™
    • Extended temperature available for 432-Mhz device
  • ARM926EJ-S™ Core
    • Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
    • DSP Instruction Extensions and Single Cycle MAC
    • ARM® Javelle® Technology
    • Embedded ICE-RT Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • 32K-Byte RAM
    • 16K-Byte ROM
    • Little Endian
  • Two Video Image Co-processors (HDVICP, MJCP) Engines
    • Support a Range of Encode and Decode Operations
    • H.264, MPEG4, MPEG2, MJPEG, JPEG, WMV9/VC1
  • Video Processing Subsystem
    • Front End Provides:
      • HW Face Detect Engine
      • Hardware IPIPE for Real-Time Image Processing
        • Resize Engine
          • Resize Images From 1/16x to 8x
          • Separate Horizontal/Vertical Control
          • Two Simultaneous Output Paths
      • IPIPE Interface (IPIPEIF)
      • Image Sensor Interface (ISIF) and CMOS Imager Interface
      • 16-Bit Parallel AFE (Analog Front End) Interface Up to 120 MHz
      • Glueless Interface to Common Video Decoders
      • BT.601/BT.656/BT.1120 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
      • Histogram Module
      • Lens distortion correction module (LDC)
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • Composite NTSC/PAL video encoder output
      • 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output
      • 3 DACs for HD Analog Video Output
      • LCD Controller
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
  • Analog-to-Digital Convertor (ADC)
  • Power Management and Real Time Clock Subsystem (PRTCSS)
    • Real Time Clock
  • 16-Bit Host-Port Interface (HPI)
  • 10/100 Mb/s Ethernet Media Access Controller (EMAC) - Digital Media
    • IEEE 802.3 Compliant
    • Supports Media Independent Interface (MII)
    • Management Data I/O (MDIO) Module
  • Key Scan
  • Voice Codec
  • External Memory Interfaces (EMIFs)
    • DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O)
    • Asynchronous16-/8-bit Wide EMIF (AEMIF)
      • Flash Memory Interfaces
        • NAND (8-/16-bit Wide Data)
        • 16 MB NOR Flash, SRAM
        • OneNAND(16-bit Wide Data)
  • Flash Card Interfaces
    • Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
    • SmartMedia/xD
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • USB Port with Integrated 2.0 High-Speed PHY that Supports
    • USB 2.0 High-Speed Device
    • USB 2.0 High-Speed Host (mini-host, supporting one external device)
    • USB On The Go (HS-USB OTG)
  • Four 64-Bit General-Purpose Timers (each configurable as two 32-bit timers)
  • One 64-Bit Watch Dog Timer
  • Two UARTs (One fast UART with RTS and CTS Flow Control)
  • Five Serial Port Interfaces (SPI) each with two Chip-Selects
  • One Master/Slave Inter-Integrated Circuit(I2C) Bus™
  • One Multi-Channel Buffered Serial Port (McBSP)
    • I2S
    • AC97 Audio Codec Interface
    • S/PDIF via Software
    • Standard Voice Codec Interface (AIC12)
    • SPI Protocol (Master Mode Only)
    • Direct Interface to T1/E1 Framers
    • Time Division Multiplexed Mode (TDM)
    • 128 Channel Mode
  • Four Pulse Width Modulator (PWM) Outputs
  • Four RTO (Real Time Out) Outputs
  • Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
  • Boot Modes
    • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, UART, USB, SPI, EMAC, or HPI
    • AEMIF (NOR and OneNAND)
  • Configurable Power-Saving Modes
  • Crystal or External Clock Input (typically 19.2 Mhz, 24 MHz, 27 Mhz or 36 MHz)
  • Flexible PLL Clock Generators
  • Debug Interface Support
    • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
    • ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory
    • Device Revision ID Readable by ARM
  • 338-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch
  • 65nm Process Technology
  • 3.3-V and 1.8-V I/O, 1.35-V Internal
  • Community Reesources

All trademarks are the property of their respective owners.

Developers can now deliver crystal clear multi-format video at up to 1080p H.264 at 30fps (encode and closed-looped decode) in their digital video designs without concerns of video format support, constrained network bandwidth, limited system storage capacity or cost with the new TMS320DM368 DaVinci™ video processors from Texas Instruments Incorporated (TI).

The DM368 is capable of achieving HD video processing at 1080p 30fps H.264 and is completely pin-to-pin compatible with the DM365 processors, using the same ARM926EJ-S core running at 432 MHz. This ARM9-based DM368 device supports production-qualified H.264BP/MP/HP, MPEG-4, MPEG-2, MJPEG and VC1/WMV9 codecs providing customers with the flexibility to select the right video codec for their application. These codecs run on independent coprocessors (HDVICP and MJCP) offloading all compression needs from the main ARM core. This allows developers to obtain optimal performance from the ARM for their applications, including their multi-channel, multi-stream and multi-format needs.

Video surveillance designers achieve greater compression efficiency to provide more storage without straining the network bandwidth. Developers of media playback and camera-driven applications, such as video doorbells, digital signage, digital video recorders, portable media players and more can take advantage of the low power consumption and can ensure interoperability, as well as product scalability by taking advantage of the full suite of codecs supported on the DM368.

Along with multi-format HD video, the DM368 also features a suite of peripherals saving developers on system cost and complexity to enable a seamless interface to most additional external devices required for video applications. The image sensor interface is flexible enough to support CCD, CMOS, and various other interfaces such as BT.565, BT1120. The DM368 also offers a high level of integration with HD display support, including three built-in 10-bit HD analog video digital-to-analog converters (DACs), DDR2/mDDR, Ethernet MAC, USB 2.0, integrated audio, host port interface (HPI), analog-to digital converter and many more features saving developers on overall system costs, as well as real estate on their circuit boards allowing for a slimmer, sleeker design.

Developers can now deliver crystal clear multi-format video at up to 1080p H.264 at 30fps (encode and closed-looped decode) in their digital video designs without concerns of video format support, constrained network bandwidth, limited system storage capacity or cost with the new TMS320DM368 DaVinci™ video processors from Texas Instruments Incorporated (TI).

The DM368 is capable of achieving HD video processing at 1080p 30fps H.264 and is completely pin-to-pin compatible with the DM365 processors, using the same ARM926EJ-S core running at 432 MHz. This ARM9-based DM368 device supports production-qualified H.264BP/MP/HP, MPEG-4, MPEG-2, MJPEG and VC1/WMV9 codecs providing customers with the flexibility to select the right video codec for their application. These codecs run on independent coprocessors (HDVICP and MJCP) offloading all compression needs from the main ARM core. This allows developers to obtain optimal performance from the ARM for their applications, including their multi-channel, multi-stream and multi-format needs.

Video surveillance designers achieve greater compression efficiency to provide more storage without straining the network bandwidth. Developers of media playback and camera-driven applications, such as video doorbells, digital signage, digital video recorders, portable media players and more can take advantage of the low power consumption and can ensure interoperability, as well as product scalability by taking advantage of the full suite of codecs supported on the DM368.

Along with multi-format HD video, the DM368 also features a suite of peripherals saving developers on system cost and complexity to enable a seamless interface to most additional external devices required for video applications. The image sensor interface is flexible enough to support CCD, CMOS, and various other interfaces such as BT.565, BT1120. The DM368 also offers a high level of integration with HD display support, including three built-in 10-bit HD analog video digital-to-analog converters (DACs), DDR2/mDDR, Ethernet MAC, USB 2.0, integrated audio, host port interface (HPI), analog-to digital converter and many more features saving developers on overall system costs, as well as real estate on their circuit boards allowing for a slimmer, sleeker design.
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技术文档

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类型 标题 下载最新的英语版本 日期
* 数据表 TMS320DM368 Digital Media System-on-Chip (DMSoC) 数据表 (Rev. C) 2011年 6月 30日
* 勘误表 TMS320DM368 Digital Media System-on-Chip Silicon Errata (Silicon Revs 1.1 & 1.2) (Rev. B) 2011年 7月 11日
应用手册 高速接口布局指南 (Rev. J) PDF | HTML 英语版 (Rev.J) PDF | HTML 2023年 3月 23日
白皮书 针对支持视频功能航拍无人机的低延迟设计注意事项_China 英语版 2016年 11月 2日
EVM 用户指南 TMS320DM368 Evaluation Module User's Guide 2016年 8月 3日
用户指南 TMS320DM36x DaVinci™ Video Processing Front End (VPFE) User's Guide (Rev. C) 2016年 6月 30日
应用手册 TMS320DM368 Power Consumption Summary (Rev. A) 2013年 9月 12日
用户指南 Powering the TMS320DM368 with the TPS650061 2012年 5月 8日
模拟设计期刊 单电源系统中单端视频到差动视频的转换 英语版 2011年 12月 2日
模拟设计期刊 模拟应用期刊 2011 第三季度 英语版 2011年 12月 2日
应用手册 DM368 NAND Flash 启动揭秘 2011年 11月 14日
用户指南 TMS320DM36x DMSoC Power Management and Real-Time Clock Subsystem User's Guide (Rev. B) 2011年 8月 3日
用户指南 TMS320DM36x DMSoC General-Purpose Input/Output User's Guide (Rev. C) 2011年 1月 19日
用户指南 TMS320DM36x DMSoC Ethernet Media Access Controller (EMAC) User's Guide (Rev. B) 2010年 12月 23日
用户指南 TMS320DM36x DMSoC Video Processing Front End User's Guide (Rev. C) 2010年 11月 12日
用户指南 TMS320DM36x DMSoC Video Processing Back End User's Guide (Rev. C) 2010年 8月 26日
用户指南 TMS320DM36x DMSoC Voice Codec User's Guide (Rev. B) 2010年 7月 30日
用户指南 TMS320DM36x DMSoC Face Detection User's Guide (Rev. A) 2010年 7月 21日
用户指南 TMS320DM36x DMSoC Asynchronous External Memory Interface User's Guide (Rev. C) 2010年 4月 23日
用户指南 TMS320DM36x DMSoC Multimedia Card/Secure Digital Card Controller User's Guide (Rev. B) 2010年 4月 23日
应用手册 Migrating from TMS320DM365 to TMS320DM368 2010年 4月 11日
更多文献资料 TMS320DM3x DaVinci Video Processors 2010年 4月 11日
用户指南 TMS320DM36x DMSoC Key Scan User's Guide (Rev. A) 2010年 3月 1日
用户指南 TMS320DM36x DMSoC Serial Peripheral Interface User's Guide (Rev. B) 2010年 3月 1日
用户指南 TMS320DM36x DMSoC Universal Host Port Interface User's Guide (Rev. A) 2009年 8月 9日
用户指南 TMS320DM36x DMSoC ARM Subsystem Reference Guide (Rev. A) 2009年 8月 7日
用户指南 TMS320DM36x DMSoC Inter-Integrated Circuit User's Guide (Rev. A) 2009年 8月 7日
用户指南 TMS320DM36x DMSoC Multichannel Buffered Serial Port User's Guide (Rev. A) 2009年 8月 7日
用户指南 TMS320DM36x DMSoC Universal Serial Bus User's Guide (Rev. A) 2009年 8月 7日
应用手册 TMS320DM36x SoC Architecture and Throughput 2009年 7月 29日
用户指南 TMS320DM36x DMSoC Analog to Digital Converter User's Guide 2009年 3月 3日
用户指南 TMS320DM36x DMSoC DDR2/mDDR Memory Controller User's Guide 2009年 3月 3日
用户指南 TMS320DM36x DMSoC Enhanced Direct Memory Access Controller User's Guide 2009年 3月 3日
用户指南 TMS320DM36x DMSoC Pulse-Width Modulator User's Guide 2009年 3月 3日
用户指南 TMS320DM36x DMSoC Real Time Out User's Guide 2009年 3月 3日
用户指南 TMS320DM36x DMSoC Timer/Watchdog Timer User's Guide 2009年 3月 3日
用户指南 TMS320DM36x DMSoC Universal Asynchronous Receiver/Transmitter User's Guide 2009年 3月 3日
应用手册 Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) 2008年 7月 17日

设计和开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

评估板

TMDXEVM368 — TMS320DM36x 评估模块

TMS320DM36x 数字视频评估模块 (DVEVM) 使开发人员可以立即开始 DaVinci™ 处理器的评估，并开始构建数字视频应用，例如 IP 监控摄像机、数码相框、数字标牌、可视门铃和其它尚未发明的便携式数字视频产品。

数字视频评估模块 (DVEVM) 允许开发人员为 ARM 编写可立即投产的应用程序代码和访问使用达芬奇 API 的 HMJCP 协处理器内核，从而立即开始针对 TMS320DM365 和 TMS320DM368 数字媒体处理器的应用开发。

TMS320DM36x 数字视频评估模块 (DM36x EVM) 包含以下组件：
  • 基于 TMS320DM368 DaVinci™ (...)
用户指南: PDF
TI.com 上无现货
调试探针

TMDSEMU200-U — XDS200 USB 调试探针

XDS200 是用于调试 TI 嵌入式器件的调试探针（仿真器）。与低成本的 XDS110 和高性能的 XDS560v2 相比，XDS200 在低成本和高性能之间实现了平衡；并在单个仓体中支持广泛的标准（IEEE1149.1、IEEE1149.7、SWD）。所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 Arm® 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的内核跟踪，则需要使用 XDS560v2 PRO TRACE。

XDS200 通过 TI 20 引脚连接器（带有适用于 TI 14 引脚、Arm Cortex® 10 引脚和 Arm 20 (...)

TI.com 上无现货
调试探针

TMDSEMU560V2STM-U — XDS560™ 软件 v2 系统跟踪 USB 调试探针

XDS560v2 是 XDS560™ 系列调试探针中性能非常出色的产品，同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。请注意，它不支持串行线调试 (SWD)。

所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 ARM 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的跟踪，需要 XDS560v2 PRO TRACE。

XDS560v2 通过 MIPI HSPT 60 引脚连接器（带有多个用于 TI 14 引脚、TI 20 引脚和 ARM 20 引脚的适配器）连接到目标板，并通过 USB2.0 高速 (480Mbps) (...)

TI.com 上无现货
调试探针

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针（仿真器）的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款，同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件，通过捕获相关器件级信息，获得准确的总线性能活动和吞吐量，并对内核和外设进行电源管理。此外，对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器，所有 XDS (...)

TI.com 上无现货
软件开发套件 (SDK)

LINUXDVSDK-DM36X — 用于 DM365、DM368 数字媒体处理器的 Linux 数字视频软件开发套件 (DVSDK)

Linux™ 数字视频软件开发套件 (DVSDK) 使 DaVinci™ 系统集成商能够快速开发基于 Linux 的多媒体应用，它们可以轻松植入达芬奇平台的不同器件中。每个 DVSDK 都包含一套预先测试的操作系统、应用程序框架和具有示例程序的编解码器库，这些程序演示了从外设流入和流出的实时音频和视频数据的解码和编码。针对具有 DSP 内核的达芬奇器件，DVSDK 提供了完整的框架，便于开发人员轻松利用 DSP 加速编解码器，而无需对 DSP 进行编程。DVSDK 完全免费，无需任何运行版税。

此版本 Linux DVSDK 4 版的正式 (GA) (...)

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软件编解码器

DM365CODECS — DM36x (DM365、DM368) 编解码器 - 软件和文档

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio, video and voice applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)

支持的产品和硬件

支持的产品和硬件

产品
数字信号处理器 (DSP)
TMS320DM365 — DaVinci 数字媒体处理器 TMS320DM368 — DaVinci 数字媒体处理器
下载选项
仿真模型

DM368 ZCE BSDL Model

SPRM495.ZIP (9 KB) - BSDL Model
下载
仿真模型

DM368 ZCE IBIS Model (Rev. A)

SPRM494A.ZIP (502 KB) - IBIS Model
下载
封装 引脚 CAD 符号、封装和 3D 模型
NFBGA (ZCE) 338 Ultra Librarian
应遵守 TI 评估类商品的标准条款与条件。

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。

支持和培训

视频