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Function General-purpose timer Iq (typ) (mA) 2 Rating Catalog Operating temperature range (°C) -40 to 105 Supply voltage (max) (V) 16 Supply voltage (min) (V) 4.5
Function General-purpose timer Iq (typ) (mA) 2 Rating Catalog Operating temperature range (°C) -40 to 105 Supply voltage (max) (V) 16 Supply voltage (min) (V) 4.5
PDIP (P) 8 92.5083 mm² 9.81 x 9.43 SOIC (D) 8 29.4 mm² 4.9 x 6
  • Timing from microseconds to hours
  • Astable or monostable operation
  • Adjustable duty cycle
  • TTL-compatible output can sink or source up to 200mA
  • On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
  • Timing from microseconds to hours
  • Astable or monostable operation
  • Adjustable duty cycle
  • TTL-compatible output can sink or source up to 200mA
  • On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

The Nx555 and Sx555 devices are precision timing circuits capable of producing accurate time delays or oscillation. In time-delay or monostable operating modes, the timed interval is controlled by a single external resistor and capacitor network. In the astable mode of operation, the frequency and duty cycle are controlled independently with two external resistors and a single external capacitor.

Each timer has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage pin (CONT). When the trigger input (TRIG) is less than the trigger level, the flip-flop is set and the output goes high. If TRIG is greater than the trigger level and the threshold input (THRES) is greater than the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) overrides all other inputs and is used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge pin (DISCH) and the ground pin (GND). Tie all unused inputs to an appropriate logic level to prevent false triggering

The output circuit is capable of sinking or sourcing current up to 200mA. Operation is specified for supplies of 5V to 15V. With a 5V supply, output levels are compatible with TTL inputs.

The Nx555 and Sx555 devices are precision timing circuits capable of producing accurate time delays or oscillation. In time-delay or monostable operating modes, the timed interval is controlled by a single external resistor and capacitor network. In the astable mode of operation, the frequency and duty cycle are controlled independently with two external resistors and a single external capacitor.

Each timer has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage pin (CONT). When the trigger input (TRIG) is less than the trigger level, the flip-flop is set and the output goes high. If TRIG is greater than the trigger level and the threshold input (THRES) is greater than the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) overrides all other inputs and is used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge pin (DISCH) and the ground pin (GND). Tie all unused inputs to an appropriate logic level to prevent false triggering

The output circuit is capable of sinking or sourcing current up to 200mA. Operation is specified for supplies of 5V to 15V. With a 5V supply, output levels are compatible with TTL inputs.

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类型 标题 下载最新的英语版本 日期
* 数据表 xx555 Precision Timers 数据表 (Rev. J) PDF | HTML 2025年 2月 11日
应用手册 Considering TI Smart DACs As an Alternative to 555 Timers PDF | HTML 2021年 9月 2日
设计指南 AC-Coupled RS-485 Design Guide 2016年 6月 15日
设计指南 Automatic Direction Control RS-485 Design Guide 2016年 6月 2日

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参考设计

TIDA-01365 — 双向 RS-485 扇出集线器参考设计

双向 RS-485 扇出集线器参考设计 (TIDA-01365) 记录和测试 RS-485 扇出集线器设计,其中 1:N 和 N:1 RS-485 信号在任意总线拓扑内外聚合。此设计还采用自动方向控制以减少微控制器上的引脚数,并采用一个直流/直流转换器,该转换器使用工业应用中常见的 24V 直流轨。
设计指南: PDF
原理图: PDF
参考设计

TIDA-01090 — RS-485 自动方向控制参考设计

TIDA-01090 参考设计可实现在 RS-485 总线中进行半双工通信,而无需其他驱动器启用/接收器启用控制。此参考设计使每个节点上使用的收发器可以在数据正在从本地微控制器 (MCU) 或通用异步接收器/发送器 (UART) 传输时自动进入传输模式,然后在数据帧达到完整状态时重新转换为接收模式。
设计指南: PDF
原理图: PDF
封装 引脚 CAD 符号、封装和 3D 模型
PDIP (P) 8 Ultra Librarian
SOIC (D) 8 Ultra Librarian

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包含信息:
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  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
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  • 持续可靠性监测
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