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TPS754

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具有电源正常指示和使能功能的 2A、超低压降稳压器

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TPS7A52 正在供货 2A、低输入电压 (1.1V)、低噪声、高精度、超低压降 (LDO) 稳压器 Lower noise performance in smaller enhanced QFN package

TPS754

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产品详情

Output options Adjustable Output, Fixed Output Iout (max) (A) 2 Vin (max) (V) 5.5 Vin (min) (V) 2.7 Vout (max) (V) 5.5 Vout (min) (V) 1.5 Fixed output options (V) 1.5, 1.8, 2.5, 3.3 Rating Catalog Noise (µVrms) 60 PSRR at 100 KHz (dB) 15 Iq (typ) (mA) 0.07 Thermal resistance θJA (°C/W) 43 Load capacitance (min) (µF) 47 Regulated outputs (#) 1 Features Enable, Power good Accuracy (%) 2 Dropout voltage (Vdo) (typ) (mV) 210 Operating temperature range (°C) -40 to 125
Output options Adjustable Output, Fixed Output Iout (max) (A) 2 Vin (max) (V) 5.5 Vin (min) (V) 2.7 Vout (max) (V) 5.5 Vout (min) (V) 1.5 Fixed output options (V) 1.5, 1.8, 2.5, 3.3 Rating Catalog Noise (µVrms) 60 PSRR at 100 KHz (dB) 15 Iq (typ) (mA) 0.07 Thermal resistance θJA (°C/W) 43 Load capacitance (min) (µF) 47 Regulated outputs (#) 1 Features Enable, Power good Accuracy (%) 2 Dropout voltage (Vdo) (typ) (mV) 210 Operating temperature range (°C) -40 to 125
HTSSOP (PWP) 20 41.6 mm² 6.5 x 6.4
  • 2-A Low-Dropout Voltage Regulator
  • Available in 1.5 V, 1.8 V, 2.5 V, 3.3 V Fixed Output and Adjustable Versions
  • Open Drain Power-On Reset With 100ms Delay (TPS752xxQ)
  • Open Drain Power-Good (PG) Status Output (TPS754xxQ)
  • Dropout Voltage Typically 210 mV at 2 A (TPS75233Q)
  • Ultralow 75-µA Typical Quiescent Current
  • Fast Transient Response
  • 2% Tolerance Over Specified Conditions for Fixed-Output Versions
  • 20-Pin TSSOP PowerPAD™ (PWP) Package
  • Thermal Shutdown Protection
  • APPLICATIONS
    • Telecom
    • Servers
    • DSP, FPGA Supplies

PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
  • 2-A Low-Dropout Voltage Regulator
  • Available in 1.5 V, 1.8 V, 2.5 V, 3.3 V Fixed Output and Adjustable Versions
  • Open Drain Power-On Reset With 100ms Delay (TPS752xxQ)
  • Open Drain Power-Good (PG) Status Output (TPS754xxQ)
  • Dropout Voltage Typically 210 mV at 2 A (TPS75233Q)
  • Ultralow 75-µA Typical Quiescent Current
  • Fast Transient Response
  • 2% Tolerance Over Specified Conditions for Fixed-Output Versions
  • 20-Pin TSSOP PowerPAD™ (PWP) Package
  • Thermal Shutdown Protection
  • APPLICATIONS
    • Telecom
    • Servers
    • DSP, FPGA Supplies

PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.

The TPS752xxQ and TPS754xxQ devices are low-dropout regulators with integrated power-on reset and power-good (PG) functions respectively. These devices are capable of supplying 2 A of output current with a dropout of 210 mV (TPS75233Q, TPS75433Q). Quiescent current is 75 µA at full load and drops down to 1 µA when the device is disabled. These devices are designed to have fast transient response for larger load current changes.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically
210 mV at an output current of 2 A for the TPS75x33Q) and is directly proportional to the output current. Additionally, because the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 75 µA over the full range of output current, 1 mA to 2 A). These two key specifications yield a significant improvement in operating life for battery-powered systems.

The device is enabled when EN is connected to a low-level input voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to less than 1 µA at TJ = +25°C.

The RESET (SVS, POR, or power on reset) output of the TPS752xxQ initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS752xxQ monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When the output reaches 95% of its regulated voltage, RESET goes to a high-impedance state after a 100-ms delay. RESET goes to a logic-low state when the regulated output voltage is pulled below 95% (that is, during an overload condition) of its regulated voltage.

The TPS754xxQ has a power good terminal (PG) as an active high, open drain output for use with a power-on reset or a low-battery indicator.

The TPS754xxQ and TPS752xxQ are offered in 1.5 V, 1.8 V, 2.5 V and 3.3 V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS754xxQ and TPS752xxQ families are available in a 20-pin TSSOP (PWP) package.

The TPS752xxQ and TPS754xxQ devices are low-dropout regulators with integrated power-on reset and power-good (PG) functions respectively. These devices are capable of supplying 2 A of output current with a dropout of 210 mV (TPS75233Q, TPS75433Q). Quiescent current is 75 µA at full load and drops down to 1 µA when the device is disabled. These devices are designed to have fast transient response for larger load current changes.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically
210 mV at an output current of 2 A for the TPS75x33Q) and is directly proportional to the output current. Additionally, because the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 75 µA over the full range of output current, 1 mA to 2 A). These two key specifications yield a significant improvement in operating life for battery-powered systems.

The device is enabled when EN is connected to a low-level input voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to less than 1 µA at TJ = +25°C.

The RESET (SVS, POR, or power on reset) output of the TPS752xxQ initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS752xxQ monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When the output reaches 95% of its regulated voltage, RESET goes to a high-impedance state after a 100-ms delay. RESET goes to a logic-low state when the regulated output voltage is pulled below 95% (that is, during an overload condition) of its regulated voltage.

The TPS754xxQ has a power good terminal (PG) as an active high, open drain output for use with a power-on reset or a low-battery indicator.

The TPS754xxQ and TPS752xxQ are offered in 1.5 V, 1.8 V, 2.5 V and 3.3 V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS754xxQ and TPS752xxQ families are available in a 20-pin TSSOP (PWP) package.
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类型 标题 下载最新的英语版本 日期
* 数据表 Fast-Transient-Response 2-A Low-Dropout Voltage Regulators 数据表 (Rev. C) 2007年 10月 19日
应用手册 LDO 噪声揭秘 (Rev. B) PDF | HTML 英语版 (Rev.B) PDF | HTML 2020年 9月 16日
应用手册 PowerPAD™ Thermally Enhanced Package (Rev. H) 2018年 7月 6日
应用手册 LDO PSRR Measurement Simplified (Rev. A) PDF | HTML 2017年 8月 9日
应用手册 简化的 LDO PSRR 测量 最新英语版本 (Rev.A) PDF | HTML 2010年 7月 28日

设计和开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

参考设计

TIDA-00207 — 符合 EN55011、工业级温度、10/100Mbps 以太网 PHY 砖型参考设计

此以太网 PHY 砖型参考设计可帮助德州仪器 (TI) 客户采用完全符合 EN5501 A 类 EMI 要求的 TI 工业以太网 PHY 收发器器件来快速设计系统并将其投向市场。此参考设计中采用一个 50 引脚接口来连接基于 32 位 Cortex M4 处理器的控制器板。该控制器板采用小外形规格设计（2 英寸 x 3 英寸），因此可轻松集成到现有产品中。 

此参考设计展示了 DP83848K 以太网 PHY 收发器器件的先进功能，支持 10/100 Base-T，并符合 IEEE 802.3 标准。整个参考设计采用单电源（采用板载稳压器的情况下为 5V，否则为 3.3V）工作。以太网 PHY (...)

设计指南: PDF
原理图: PDF
参考设计

TIDA-00928 — 采用光纤或双绞线接口、符合 EMI/EMC 标准的 10/100Mbps 以太网砖型参考设计

这一以太网砖型参考设计提供了一种简化的解决方案，因而无需多个铜线或光纤接口板。该设计采用小尺寸、低功耗的 10/100Mbps 以太网收发器来减小板尺寸，提供成本优化且可扩展的解决方案，降低高温工业应用的功耗。DP83822 提供发送和接收数据所需的所有物理层功能—无论是通过标准双绞线电缆，还是连接至外部光纤（SC 或 ST 或 SFP）收发器。此设计可采用固定或可编程的 LDO 为模拟和 IO 电源配置不同的供电水平。砖型结构通过内部 MAC 连接到 TM4C129X TIVA™ MCU。此设计依照 IEC61000-4 标准级别 4 针对辐射发射、ESD 和 EFT 进行了测试。
设计指南: PDF
原理图: PDF
封装 引脚 CAD 符号、封装和 3D 模型
HTSSOP (PWP) 20 Ultra Librarian
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包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
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