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模数转换器 (ADC)
高速 ADC (≥10MSPS)

ADC08B200-Q1

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8 位 200MSPS 数模转换器 (ADC) - 符合汽车应用标准

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ADC08B200-Q1

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产品详情

Sample rate (max) (Msps) 200 Resolution (bps) 8 Number of input channels 1 Interface type Parallel CMOS Analog input BW (MHz) 500 Features Low Power Rating Automotive Peak-to-peak input voltage range (V) 1.6 Power consumption (typ) (mW) 543 Architecture Pipeline SNR (dB) 47 ENOB (bit) 7.4 SFDR (dB) 56 Operating temperature range (°C) -40 to 105 Input buffer No
Sample rate (max) (Msps) 200 Resolution (bps) 8 Number of input channels 1 Interface type Parallel CMOS Analog input BW (MHz) 500 Features Low Power Rating Automotive Peak-to-peak input voltage range (V) 1.6 Power consumption (typ) (mW) 543 Architecture Pipeline SNR (dB) 47 ENOB (bit) 7.4 SFDR (dB) 56 Operating temperature range (°C) -40 to 105 Input buffer No
TQFP (PFB) 48 81 mm² 9 x 9
  • Single-Ended Input
  • Selectable Capture Buffer Size
  • PLL for Clock Multiplication
  • Reference Ladder Top and Bottom Accessible
  • Linear Power Scaling with Sample Rate
  • FPGA Training Pattern
  • AEC-Q100 Grade 2 Qualified
  • Power-Down Feature

Key Specifications

    (PLL Bypassed)

  • Resolution 8 Bits
  • Maximum Sampling Frequency 200 MSPS (min)
  • DNL ±0.4 LSB (typ)
  • ENOB (fIN= 49 MHz) 7.2 bits (typ)
  • THD (fIN= 49 MHz) −53 dBc (typ)
  • Power Consumption
    • Operating (50 MHz) Input 2 mW / Msps (typ)
    • Power Down 2.15 mW (typ)

All trademarks are the property of their respective owners.

  • Single-Ended Input
  • Selectable Capture Buffer Size
  • PLL for Clock Multiplication
  • Reference Ladder Top and Bottom Accessible
  • Linear Power Scaling with Sample Rate
  • FPGA Training Pattern
  • AEC-Q100 Grade 2 Qualified
  • Power-Down Feature

Key Specifications

    (PLL Bypassed)

  • Resolution 8 Bits
  • Maximum Sampling Frequency 200 MSPS (min)
  • DNL ±0.4 LSB (typ)
  • ENOB (fIN= 49 MHz) 7.2 bits (typ)
  • THD (fIN= 49 MHz) −53 dBc (typ)
  • Power Consumption
    • Operating (50 MHz) Input 2 mW / Msps (typ)
    • Power Down 2.15 mW (typ)

All trademarks are the property of their respective owners.

The ADC08B200 is a high speed analog-to-digital converter (ADC) with an integrated capture buffer. The 8-bit, 200 MSPS A/D core is based upon the proven ADC08200 with integrated track-and-hold and is optimized for low power consumption. This device contains a selectable size capture buffer of up to 1,024 bytes that allows fast capture of an input signal with a slower readout rate. An on-chip clock PLL circuit provides the option of on-chip clock rate multiplication to provide the high speed sampling clock.

The ADC08B200 is resistant to latch-up and the outputs are short-circuit proof. The top and bottom of the ADC08B200's reference ladder are available for connections, enabling a wide range of input possibilities. The digital outputs are TTL/CMOS compatible with a separate output power supply pin to support interfacing with 2.7V to 3.3V logic. The digital inputs and outputs are low voltage TTL/CMOS compatible and the output data format is straight binary.

The ADC08B200Q runs on an Automotive Grade Flow and is AEC-Q100 Grade 2 Qualified.

The ADC08B200 is offered in a 48-pin plastic package (TQFP) and is specified over the extended industrial temperature range of −40°C to +105°C. An evaluation board is available to assist in the easy evaluation of the ADC08B200.

The ADC08B200 is a high speed analog-to-digital converter (ADC) with an integrated capture buffer. The 8-bit, 200 MSPS A/D core is based upon the proven ADC08200 with integrated track-and-hold and is optimized for low power consumption. This device contains a selectable size capture buffer of up to 1,024 bytes that allows fast capture of an input signal with a slower readout rate. An on-chip clock PLL circuit provides the option of on-chip clock rate multiplication to provide the high speed sampling clock.

The ADC08B200 is resistant to latch-up and the outputs are short-circuit proof. The top and bottom of the ADC08B200's reference ladder are available for connections, enabling a wide range of input possibilities. The digital outputs are TTL/CMOS compatible with a separate output power supply pin to support interfacing with 2.7V to 3.3V logic. The digital inputs and outputs are low voltage TTL/CMOS compatible and the output data format is straight binary.

The ADC08B200Q runs on an Automotive Grade Flow and is AEC-Q100 Grade 2 Qualified.

The ADC08B200 is offered in a 48-pin plastic package (TQFP) and is specified over the extended industrial temperature range of −40°C to +105°C. An evaluation board is available to assist in the easy evaluation of the ADC08B200.
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类型 标题 下载最新的英语版本 日期
* 数据表 ADC08B200 / ADC08B200Q 8-Bit, 200 MSPS A/D Converter with Capture Buffer 数据表 (Rev. F) 2013年 4月 2日
应用手册 Adaptive Speed Control for Automotive Systems 2007年 11月 20日

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  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
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  • 鉴定摘要
  • 持续可靠性监测
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